Programming cellular permutation networks through decomposition of symmetric groups
IEEE Transactions on Computers
Performing BMMC Permutations in Two Passes through the Expanded Delta Network and MasPar MP-2
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Test Generation for Path-Delay Faults in One-dimensional Iterative Logic Arrays
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Logic Design Using EFL Structures
IEEE Transactions on Computers
Interconnection Networks from Three State Cells
IEEE Transactions on Computers
Cellular Logic-in-Memory Arrays
IEEE Transactions on Computers
Mesh-Connected Computers with Broadcasting
IEEE Transactions on Computers
IEEE Transactions on Computers
Routing Algorithms for Cellular Interconnection Arrays
IEEE Transactions on Computers
The DIMOND: A Component for the Modular Construction of Switching Networks
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
A study of the data commutation problems in a self-repairable multiprocessor
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Programmable indexing networks
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
The architecture of a large associative processor
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
Magnetic bubble computer systems
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
A study of fault tolerance techniques for associative processors
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
Interconnection networks: a survey and assessment
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
IEEE Transactions on Computers
Testable Sequential Cellular Arrays
IEEE Transactions on Computers
Decomposition of Permutation Networks
IEEE Transactions on Computers
IEEE Transactions on Computers
The topology of cellular partitioning networks
IEEE Transactions on Computers
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Abstract A class of networks is described that has the capability of permuting in an arbitrary manner a set of n digital input lines onto a set of n digital output lines. The circuitry of the networks is arranged in cellular form, i. e., in a two-dimensional iterative pattern with mainly local intercell connections, where the basic cell behaves as a reversing switch with a single memory flip-flop. Various network forms are described, differing in the number of cells needed, in the shape of the array, and in the length and regularity of intercell connections. Also discussed are some ways of setting up the array to achieve a desired permutation.