Test Generation for Path-Delay Faults in One-dimensional Iterative Logic Arrays

  • Authors:
  • Nabil M. Abdulrazzaq;Sandeep K. Gupta

  • Affiliations:
  • -;-

  • Venue:
  • ITC '00 Proceedings of the 2000 IEEE International Test Conference
  • Year:
  • 2000

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Abstract

We propose a test generation method for path-delay faultsin combinational iterative logic arrays (ILAs). The number of paths as well as the number of critical paths in ILAs cangrow exponentially with the number of stages. Existing-pathdelaytest generation techniques explicitly target each selected path and can not generate tests for ILAs with reasonable numbers of stages, e.g., 16 and 32. The proposed method overcomes this difficulty by implicitly targeting all testable paths and can generate tests for ILAs of arbitrary size and guarantees coverage of all testable faults.The proposed method also drastically decreases the testdata volume to be stored in the high-speed memories in theprobe unit of the tester by generating tests in the form of asmall number of expressions. This is of great benefit sincethe ability to store large volumes of test data is a significantlygreater limiting factor than the time required to apply thetests. Finally, for most ILAs, this method produces acompact set of tests.