NEST: A non-enumerative test generation method for path delay faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
A satisfiability-based test generator for path delay faults in combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Test generation for path delay faults based on learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Theory of Computation: A Primer
Theory of Computation: A Primer
Computer Organization
DAC '77 Proceedings of the 14th Design Automation Conference
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
IEEE Design & Test
Cellular Interconnection Arrays
IEEE Transactions on Computers
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We propose a test generation method for path-delay faultsin combinational iterative logic arrays (ILAs). The number of paths as well as the number of critical paths in ILAs cangrow exponentially with the number of stages. Existing-pathdelaytest generation techniques explicitly target each selected path and can not generate tests for ILAs with reasonable numbers of stages, e.g., 16 and 32. The proposed method overcomes this difficulty by implicitly targeting all testable paths and can generate tests for ILAs of arbitrary size and guarantees coverage of all testable faults.The proposed method also drastically decreases the testdata volume to be stored in the high-speed memories in theprobe unit of the tester by generating tests in the form of asmall number of expressions. This is of great benefit sincethe ability to store large volumes of test data is a significantlygreater limiting factor than the time required to apply thetests. Finally, for most ILAs, this method produces acompact set of tests.