Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Testability properties of multilevel logic networks derived from binary decision diagrams
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
NEST: A non-enumerative test generation method for path delay faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Compact test sets for digital logic circuits
Compact test sets for digital logic circuits
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Efficient testing of clock regenerator circuits in scan designs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reduction of Number of Paths to be Tested in Delay Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability
EDTC '96 Proceedings of the 1996 European conference on Design and Test
9.3 Improving Path Delay Fault Testability by Path Removal
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Generation for Path-Delay Faults in One-dimensional Iterative Logic Arrays
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A new classification of path-delay fault testability in terms of stuck-at faults
Journal of Computer Science and Technology
| Hi-index | 14.98 |
The problems involved in handling large numbers of path delay faults were alleviated in previous works, by developing fault simulation and test generation procedures that do not require paths to be explicitly considered. Thus, the methods developed allow the set of all path delay faults to be targeted during test generation and fault simulation. With the problems related to the number of paths removed, a new limiting factor in test generation for path delay faults is revealed, namely, the number of tests required to detect all path delay faults. In this work, the problems related to the number of tests are investigated. A procedure for computing a lower bound on the number of tests is described, and methods for synthesizing circuits with reduced lower bounds on the numbers of tests are developed. Experimental results are presented to demonstrate various aspects of the problem