Necessary and sufficient conditions for robust delay-fault testability of combinational logic circuits

Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference

Robust delay-fault test generation and synthesis for testability under a standard scan design methodology

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference

A synthesis-based test generation and compaction algorithm for multifaults

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference

NEST: A non-enumerative test generation method for path delay faults in combinational circuits

DAC '93 Proceedings of the 30th international Design Automation Conference

Delay fault coverage and performance tradeoffs

DAC '93 Proceedings of the 30th international Design Automation Conference

On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits

IEEE Transactions on Computers

Generation of High Quality Tests for Robustly Untestable Path Delay Faults

IEEE Transactions on Computers