Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
NEST: A non-enumerative test generation method for path delay faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Random pattern testable logic synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Built-in test generation for synchronous sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A synthesis procedure for flexible logic functions
Proceedings of the conference on Design, automation and test in Europe
On output response compression in the presence of unknown output values
Proceedings of the 39th annual Design Automation Conference
Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability
EDTC '96 Proceedings of the 1996 European conference on Design and Test
9.3 Improving Path Delay Fault Testability by Path Removal
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
IEEE Transactions on Computers
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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