IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
On the distribution of fault coverage and test length in random testing of combinational circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Don't cares in multi-level network optimization
Don't cares in multi-level network optimization
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Random Testability of Redundant Circuits
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Can Redundancy Enhance Testability?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Logic Partitioning and Resynthesis for Testability
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
LOT: logic optimization with testability—new transformations using recursive learning
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BETSY: synthesizing circuits for a specified BIST environment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Test Point Insertion Algorithm for Mixed-Signal Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
| Hi-index | 0.00 |
Previous procedures for synthesis of testable logic guarantee that all faults in the synthesized circuits are detectable. However, the detectability of many faults in these circuits can be very low leading to poor random pattern testability. A new procedure to perform logic synthesis that synthesizes random pattern testable multilevel circuits is proposed. Experimental results show that the circuits synthesized by the proposed procedure tstfx are significantly more random pattern testable and smaller than those synthesized using its counterpart fast_extract (fx) in SIS. The proposed synthesis procedure design circuits that require only simple random pattern generators in built-in self-test, thereby obviating the need for complex BIST circuitry.