Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Test Length for Pseudorandom Testing
IEEE Transactions on Computers
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
IEEE Transactions on Computers
Test Length in a Self-Testing Environment
IEEE Design & Test
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
Test Length for Pseudorandom Testing
IEEE Transactions on Computers
On Computing Signal Probability and Detection Probability of Stuck-At Faults
IEEE Transactions on Computers
Analysis of Detection Probability and Some Applications
IEEE Transactions on Computers
On the distribution of fault coverage and test length in random testing of combinational circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Random pattern testable logic synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
Tests for path delay faults vs. tests for gate delay faults: how different they are
EURO-DAC '94 Proceedings of the conference on European design automation
Fault Coverage and Test Length Estimation for Random Pattern Testing
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Proceedings of the 14th international symposium on Systems synthesis
The Reliability of Approximate Testability Measures
IEEE Design & Test
Built-In Self-Test of the Macrolan Chip
IEEE Design & Test
Test-Pattern Generation Based on Reed-Muller Coefficients
IEEE Transactions on Computers
Fault coverage of a long random test sequence estimated from a short simulation
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
How Seriously Do You Take Possible-Detect Faults?
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A probabilistic fault model for analog faults
EURO-DAC '91 Proceedings of the conference on European design automation
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Antirandom testing: a distance-based approach
VLSI Design
GLFSR: a new test pattern generator for built-in-self-test
ITC'94 Proceedings of the 1994 international conference on Test
Microprocessor testing by instruction sequences derived from random patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Multiple distributions for biased random test patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Circular BIST with partial scan
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
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Algorithmic test generation for high fault coverage is an expensive and time-consuming process. As an alternative, circuits can be tested by applying pseudorandom patterns generated by a linear feedback shift register (LFSR). Although no fault simulation is needed, analysis of pseudorandom testing requires the circuit detectability profile.