IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Design of an Efficient Weighted-Random-Pattern Generation System
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Fast Marker Based C-Arm Pose Estimation
MICCAI '08 Proceedings of the 11th International Conference on Medical Image Computing and Computer-Assisted Intervention, Part II
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In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. A synthesis procedure for this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators. The experiment result shows that compared with the non-configurable 2-D LFSR, the average number of flip-flops is reduced by 79% for five benchmark circuits. The average number of faults detected by the configurable 2-D LFSR is 9.27% higher than that of the conventional LFSR and 0.57% higher than that of the non-configurable 2-D LFSR.