Circular BIST with partial scan

Authors:
M. M. Pradhan;E. J. O'Brien;S. L. Lam;J. Beausang
Affiliations:
AT&T, Engineering Research Center, Princeton, NJ;AT&T, Engineering Research Center, Princeton, NJ;AT&T, Engineering Research Center, Princeton, NJ;Deparmtent of Electrical Engineering, The University of Rochester, Rochester, NY
Venue:
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Year:
1988

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Abstract

A BIST (Built-In Self-Test) methodology that uses the circular BIST technique to perform a random test of sequential logic circuits is presented. The fault coverage obtained using this technique is supplemented by deterministic tests that are presented to the CUT (Circuit Under Test) by configuring the circular path as a partial scan chain. A CAD (Computer-Aided Design) tool for automating this methodology is described, a variety of heuristics for picking which flip-flops should be included in the circular path are evaluated and experimental results are presented.