Algorithms for Detection of Faults in Logic Circuits
IEEE Transactions on Computers
Derivation of optimum test sequencies for sequential machines
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
A Design Diversity Metric and Reliability Analysis for Redundant Systems
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design for Testability A Survey
IEEE Transactions on Computers
Sequential Circuit Output Probabilities From Regular Expressions
IEEE Transactions on Computers
Minimal Detecting Transition Sequences: Application to Random Testing
IEEE Transactions on Computers
Fault-Tolerant Computing: A Introduction
IEEE Transactions on Computers
Testing by Feedback Shift Register
IEEE Transactions on Computers
Detection of Single Intermittent Faults in Sequential Circuits
IEEE Transactions on Computers
Estimating the latent time of fault detection in finite automaton tested in real time
Automation and Remote Control
Optimal periodic testing policy for circuit with self-testing
Computers & Mathematics with Applications
Circular BIST with partial scan
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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In digital circuits there is typically a delay between the occurrence of a fault and the first error in the output. This delay is the error latency of the fault. A model to characterize the error latency of a fault in a sequential circuit is presented.