On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Fault Latencies of Concurrent Checking FSMs
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Self-Checking of FPGA-Based Control Units
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
The Error Latency of a Fault in a Sequential Digital Circuit
IEEE Transactions on Computers
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The notions of potential and real latent times of fault detection in finite automata were introduced. The potential latent time is the minimal theoretical time of automaton fault detection, the real time is defined as the time of fault manifestation at a certain point. A method for determination of the statistical characteristics of both times for the automaton tested in the course of its real operation was proposed. It is based on selection of the trajectories of the Markov chain describing behavior of the operable and faulty automata. Additionally, a method for determination of the upper bound of the mean latent time in the case of limited information about the automaton characteristics was proposed.