An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers
The Error Latency of a Fault in a Sequential Digital Circuit
IEEE Transactions on Computers
About Random Fault Detection of Combinational Networks
IEEE Transactions on Computers
Signature Analysis for Multiple-Output Circuits
IEEE Transactions on Computers
Aliasing errors in linear automata used as multiple-input signature analyzers
IBM Journal of Research and Development
Identification of failing tests with cycling registers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A vote in favor of fault simulation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
| Hi-index | 14.98 |
A compact testing method called feedback shift register testing (FSR testing) is presented and its properties, concerning detection and diagnosis, are given. The new notion of distinction potential is introduced. The proposed method is shown to have the maximum resolution and the maximum distinction potential that can be found for an m-bit signature.