Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Aliasing Errors in Signature in Analysis Registers
IEEE Design & Test
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Testing by Feedback Shift Register
IEEE Transactions on Computers
The Weighted Syndrome Sums Approach to VLSI Testing
IEEE Transactions on Computers
IEEE Design & Test
IEEE Transactions on Computers
Notes on Multiple Input Signature Analysis
IEEE Transactions on Computers
Counter-Based Compaction: Delay and Stuck-Open Faults
IEEE Transactions on Computers
DESIGN OF COMPACTORS FOR SIGNATURE-ANALYZERS IN BUILT-IN SELF-TEST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IEEE Transactions on Computers
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