Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
A unified view of test compression methods
IEEE Transactions on Computers
Aliasing errors in linear automata used as multiple-input signature analyzers
IBM Journal of Research and Development
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
IWDC '02 Proceedings of the 4th International Workshop on Distributed Computing, Mobile and Wireless Computing
Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An efficient comparative concurrent Built-In Self-Test technique
ATS '95 Proceedings of the 4th Asian Test Symposium
DC control and observation structures for analog circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
An improved output compaction technique for built-in self-test in VLSI circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Novel BIST Architecture With Built-in Self Check
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A practical approach to instruction-based test generation for functional modules of VLSI processors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
13.1 A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Emulating static faults using a Xilinx based emulator
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Investigating some special sequence lengths generated in an external exclusive-NOR type LFSR
Computers and Electrical Engineering
Test Generation for Model-Based Diagnosis
Proceedings of the 2008 conference on ECAI 2008: 18th European Conference on Artificial Intelligence
On multiple fault coverage and aliasing probability measures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A test and maintenance controller for a module containing testable chips
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Altera max plus II development environment in fault simulation and test implementation of embedded
IWDC'04 Proceedings of the 6th international conference on Distributed Computing
Implementation of embedded cores-based digital devices in JBits java simulation environment
CIT'04 Proceedings of the 7th international conference on Intelligent Information Technology
WSEAS Transactions on Circuits and Systems
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A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuitresponse. This article surveys the structures that are used to implement these self-test functions. The various techniquesused to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/Obonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designsuse linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shiftregister designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysisare presented.