A test and maintenance controller for a module containing testable chips

Authors:
Melvin A. Breuer;Jung-Cheun Lien
Affiliations:
University of Southern California, Department of EE-Systems, Los Angeles, CA;University of Southern California, Department of EE-Systems, Los Angeles, CA
Venue:
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Year:
1988

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Abstract

A design of a module test and maintenance controller (MMC) is presented in this paper. Driven by structured test programs, an MMC is able to test every chip in a module via an ETM-BUS or a Boundary Scan bus. More than one test bus can be controlled by an MMC. MMC processor instructions, when executed, produce bus timing sequences which control a chip's BIT structures. The proposed MMC is a universal design. The difference between MMCs on different modules is the test programs which they executed and the number of test busses they control. Performance analysis indicates that either a RISC-type processor or DMA controller is required in the MMC. Some self-test features of the MMC are also presented.