System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A test and maintenance controller for a module containing testable chips
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuitresponse. This article surveys the structures that are used to implement these self-test functions. The various techniquesused to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/Obonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designsuse linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shiftregister designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysisare presented.