Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test and Debug Strategy of the PNX8525 Nexperia" Digital Video Platform System Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
InTeRail: A Test Architecture for Core-Based SOCs
IEEE Transactions on Computers
System-level testability of hardware/software systems
ITC'94 Proceedings of the 1994 international conference on Test
Testing and diagnosis of interconnects using boundary scan architecture
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A realistic self-test machine for static random access memories
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A test and maintenance controller for a module containing testable chips
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
| Hi-index | 0.00 |
Historically, IC testing and board testing have been considered two separate subjects. However, today's increasing complexityin both design and technology has given rise to a number of efforts to produce a consistent test strategy that smoothly couplesboth types of testing. This article describes one such effort by Philips, a design for testability methodology for semicustomVLSI circuits. The methodology is based on the partitioning of a design into testable macros, hence the term ?macro testing.?The challenges in this approach are the partitioning itself, the selection of a test technique suited to the separate macrosand the chip's architecture, the execution of a macro test independent of its environment, and the assembly of macro testsinto a chip test.