A realistic self-test machine for static random access memories

Authors:
Rob Dekker;Frans Beenker;Loek Thijssen
Affiliations:
Philips Research Laboratories, Eindhoven, The Netherlands;Philips Research Laboratories, Eindhoven, The Netherlands;Department of Electrical Engineering, Delft University of Technology, Delft, The Netherlands
Venue:
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Year:
1988

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Abstract

In this paper the specification and design implementation of a self-test machine for Static Random Access Memories (SRAMs) is presented. The design contains several improvements over existing self-test machines: 1. The test algorithm implemented by the selftest machine has proven to have excellent fault detection capabilities [1]. 2. The structure of the self-test machine is independent of address and data scrambling. 3. The self-test machine generates data backgrounds on-chip and is therefore suitable for both bit oriented and word oriented SRAMs. 4. It has an option for a data retention test. 5. It is suitable for both embedded SRAMs and stand-alone SRAMs and fits perfectly in a boundary-scan environment. 6. Due to the regular and symmetric structure of the test algorithm the silicon overhead is kept small (3% for a 16K synchronous SRAM).