An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers
Accumulator Compression Testing
IEEE Transactions on Computers - The MIT Press scientific computation series
Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer
IEEE Transactions on Computers
Signature Analysis for Multiple-Output Circuits
IEEE Transactions on Computers
A unified view of test compression methods
IEEE Transactions on Computers
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
IEEE Transactions on Computers
IEEE Transactions on Computers
On minimizing memory in systolic arrays for the dynamic time warping algorithm
Integration, the VLSI Journal
Board-level diagnosis by signature analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On multiple fault coverage and aliasing probability measures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A new framework for designing & analyzing BIST techniques: computation of exact aliasing probability
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A realistic self-test machine for static random access memories
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An advanced data compaction approach for test-during burn- in
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Optimal scheduling of signature analysis for VLSI testing
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
The non-linear feedback shift-register as a built-in self-test (BIST) resource
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Can we eliminate fault escape in self testing by polynomial division (signature analysis)?
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Higher certainty of error coverage by output data modification
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Design of test pattern generators for built-in test
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
A vote in favor of fault simulation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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A linear feedback shift register can be used to compress a serial stream of test result data. The compressed erroneous bit stream caused by a fault is said to form the "signature" of the fault. Since the bit stream is compressed, however, it is possible for an erroneous bit stream and the correct one to result in the same signature.