Optimal scheduling of signature analysis for VLSI testing

  • Authors:

  • Y.-H. Lee;C. M. Krishna

  • Affiliations:

  • IBM T.J. Watson Research Center, Yorktown Heights, NY;Electrical and Computer Engg., University of Massachusetts, Amherst, MA

  • Venue:
  • ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
  • Year:
  • 1988

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Abstract

Signature analysis has become a popular way of testing VLSI circuits. We present a simple algorithm to optimally schedule the signature analyses. The objective is to minimize the mean testing time per VLSI circuit.