Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
On computing optimized input probabilities for random tests
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Multiple fault diagnosis in combinational networks
DAC '79 Proceedings of the 16th Design Automation Conference
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
Measures of the Effectiveness of Fault Signature Analysis
IEEE Transactions on Computers
Multiple Fault Detection in Programmable Logic Arrays
IEEE Transactions on Computers
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
IEEE Transactions on Computers
IEEE Design & Test
A method of fault analysis for test generation and fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The paper contains a comparative study of different methods of calculating multiple fault coverage and aliasing probability measures. The interpretation, accuracy, and applicability of the measures are discussed.