A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Multiple fault diagnosis in combinational networks.
Multiple fault diagnosis in combinational networks.
Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
Generic Fault Characterizations for Table Look-Up Coverage Bounding
IEEE Transactions on Computers
Redundancy Testing in Combinational Networks
IEEE Transactions on Computers
On the Design of Multiple Fault Diagnosable Networks
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
On the Design of Logic Networks with Redundancy and Testability Considerations
IEEE Transactions on Computers
Resolution-Oriented Fault Interrelationships in Combinational Logic Networks
IEEE Transactions on Computers
A Nand Model ror Fault Diagnosis in Combinational Logic Networks
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
Spectral Signature Testing of Multiple Stuck-at Faults in Irredundant Combinational Networks
IEEE Transactions on Computers
The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's
IEEE Transactions on Computers
Logic Test Pattern Generation Using Linear Codes
IEEE Transactions on Computers
Exhaustive Test Pattern Generation with Constant Weight Vectors
IEEE Transactions on Computers
Iterative exhaustive pattern generation for logic testing
IBM Journal of Research and Development
On multiple fault coverage and aliasing probability measures
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
An analysis of the multiple fault detection capabilities of single stuck-at fault test sets
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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A general theory is presented in this paper to quantitatively predict the multiple fault coverage capability of single fault detection test sets in combinational circuits. The theory is unique in that it provides greatest lower bounds on the coverage capability of all possible circuits of concern by a simple table-look-up process. All the results known so far in this area are seen to be special cases of the theory. The more important contribution of the theory, however, is seen in its predictions made for reconvergent internal fan-out circuits. Most unexpectedly, the multiple fault coverage of such circuits by single fault test sets is discovered to be extremely precarious. Such results clearly have alarming implications in LSI and VLSI testing.