On the Design of Logic Networks with Redundancy and Testability Considerations

Authors:
R. Dandapani;S. M. Reddy
Affiliations:
Department of Engineering Technology, University of Iowa;-
Venue:
IEEE Transactions on Computers
Year:
1974

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Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets

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Fault Diagnosis of MOS Combinational Networks

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Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains

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A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays

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Minimal Redundant Logic for High Reliability and Irredundant Testability

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On the Properties of Irredundant Logic Networks

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Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results

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Multiple Fault Testing of Large Circuits by Single Fault Test Sets

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Abstract

The presence of redundancy in combinational networks increases the cardinality of the test set to detect all stuck-at-faults. A solution to this problem is to identify and remove all redundancies in the networks before deriving test sets. It is shown in this paper that the identification of redundancy in arbitrary combinational networks is an extremely tedious problem.