Logic design automation of MOS combinational networks with fan-in, fan-out constraints
DAC '78 Proceedings of the 15th Design Automation Conference
Logic design automation of diagnosable MOS combinational logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
AUTOMATIC SYSTEM LEVEL TEST GENERATION AND FAULT LOCATION FOR LARGE DIGITAL SYSTEMS
DAC '78 Proceedings of the 15th Design Automation Conference
Synthesis of Networks with a Minimum Number of Negative Gates
IEEE Transactions on Computers
Synthesis Algorithms for 2-level MOS Networks
IEEE Transactions on Computers
Synthesis of Diagnosable FET Networks
IEEE Transactions on Computers
Minimization of Logic Networks Under a Generalized Cost Function
IEEE Transactions on Computers
Fault Detection in Fanout-Free Combinational Networks
IEEE Transactions on Computers
Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results
IEEE Transactions on Computers
Derivation of Minimum Test Sets for Unate Logical Circuits
IEEE Transactions on Computers
On the Design of Logic Networks with Redundancy and Testability Considerations
IEEE Transactions on Computers
Easily Testable Realizations ror Logic Functions
IEEE Transactions on Computers
Complete Test Sets for Logic Functions
IEEE Transactions on Computers
A Design Procedure for Fault-Locatable Switching Circuits
IEEE Transactions on Computers
Detection of Multiple Faults in Combinational Logic Networks
IEEE Transactions on Computers
Derivation of Minimal Test Sets for Monotonic Logic Circuits
IEEE Transactions on Computers
MOS test pattern generation using path algebras
IEEE Transactions on Computers
Logic design automation of MOS combinational networks with fan-in, fan-out constraints
DAC '78 Proceedings of the 15th Design Automation Conference
Voting model based diagnosis of bridging faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Spectral Fault Signatures for Internally Unate Combinational Networks
IEEE Transactions on Computers
Extraction and simulation of realistic CMOS faults using inductive fault analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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The increasing difficulties in testing large logic networks have generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks with and without fan-in, fan-out constraints were described in previous papers by the authors. In this two-part series, we discuss the testing of these designed networks.