Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Optimal layout to avoid CMOS stuck-open faults
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Multiple Stuck-Open Fault Detection in CMOS Logic Circuits
IEEE Transactions on Computers - Fault-Tolerant Computing
On fault detection in CMOS logic networks
DAC '83 Proceedings of the 20th Design Automation Conference
Designing CMOS Circuits for Switch-Level Testability
IEEE Design & Test
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Fault Diagnosis of MOS Combinational Networks
IEEE Transactions on Computers
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Design & Test
A CMOS fault extractor for inductive fault analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models
Integration, the VLSI Journal
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On applying non-classical defect models to automated diagnosis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Switch-level bridging fault simulation in the presence of feedbacks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect-oriented test quality assessment using fault sampling and simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test Challenges in Nanometer Technologies
ETW '00 Proceedings of the IEEE European Test Workshop
Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods
ETW '00 Proceedings of the IEEE European Test Workshop
Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods
ETW '00 Proceedings of the IEEE European Test Workshop
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
Journal of Electronic Testing: Theory and Applications
Self-Checking Scheme for Very Fast Clocks' Skew Correction
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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Inductive Fault Analysis (IFA) is a systematic method for determining what faults are likely to occur in a VLSI circuit. It takes into account the circuit's technology, fabrication defect statistics and physical layout. This "inductive" approach of characterizing faults, by drawing conclusions based on analyzing the particulars of low-level fault-inducing mechanisms, departs from the traditional approach of simply assuming a convenient high-level fault model. FXT is a software tool which implements Inductive Fault Analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by the single line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.