A novel algorithm to extract two-node bridges
Proceedings of the 37th Annual Design Automation Conference
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Extraction and simulation of realistic CMOS faults using inductive fault analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Low-Power and testable circuit synthesis using Shannon decomposition
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis of Resistive Open Defects in Drowsy SRAM Cells
Journal of Electronic Testing: Theory and Applications
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Scaling transistor feature size allows greater density, higher performance and lower cost. The unrelenting pursuit of device scaling has enabled MOS gate dimensions to be reduced from 10m in the 1970's to a present day size of 0.1m. Conventional scaling of gate oxide thickness, source/drain extension, junction depths, and gate lengths have brought about several new technology issues invalidating some earlier methods for testing ICs. To enable testing devices into the 21st century, new approaches are required in both test and design for testability. In this paper, we will define the problems that arise with device scaling such as Gate Oxide leakage, sub-threshold leakage, power density, electromigration, and soft error problems in qualitative and quantitative terms. The later half of the paper deals with some of the solutions being pursued at Intel.