Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An experimental analysis of spot defects in SRAMs: realistic fault models and tests
ATS '00 Proceedings of the 9th Asian Test Symposium
Test Challenges in Nanometer Technologies
ETW '00 Proceedings of the IEEE European Test Workshop
The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Functional Memory Faults: A Formal Notation and a Taxonomy
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
SRAM Leakage Suppression by Minimizing Standby Supply Voltage
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution
ATS '04 Proceedings of the 13th Asian Test Symposium
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
Journal of Electronic Testing: Theory and Applications
Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies
Fast detection of data retention faults and other SRAM cell open defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault Modeling and Detection for Drowsy SRAM Caches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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New fault behaviors can emerge with the introduction of a drowsy mode to SRAMs. In this work, we show that, in addition to the data-retention faults that can occur during the drowsy mode, open defects in SRAM cells can also result in new fault behaviors when a memory is accessed immediately after wake-up. We first describe these new read-after-drowsy (RAD) fault behaviors and derive their corresponding fault primitives (FPs). Then, we propose a new March test, called March RAD, by inserting drowsy operations to a traditional test algorithm. Finally, the impact of the standby supply voltage on triggering the drowsy faults in SRAM cells is investigated. It is shown that, as the supply voltage is reduced in the drowsy mode to further cut down leakage, open defects with a parasitic resistance as small as 100 K 驴 begin to cause faults.