The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance

  • Authors:
  • Li Ding;Pinaki Mazumder

  • Affiliations:
  • -;-

  • Venue:
  • VLSID '03 Proceedings of the 16th International Conference on VLSI Design
  • Year:
  • 2003

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Abstract

In this paper, we provide an analytical framework tostudy the inter-cell and intra-cell bit-line coupling when itis superimposed with the ground bounce effect and showhow those noises impair the performance of SRAM. Theimpact of noises is expressed in term of a coupling noisedegradation factor and a ground bounce degradation factor.We have used analytical techniques to reduce the governingnonlinear ordinary differential equations to some manageableform and have derived very simple formulas for thosedegradation factors. Experiments have shown that the resultsobtained using the derived simple formulas are in goodagreement with HSPICE simulation.