Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests
Journal of Electronic Testing: Theory and Applications
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs
IEEE Transactions on Computers
Simulation Based Analysis of Temperature Effect on the Faulty Behavior of Embedded DRAMs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Soft Faults and the Importance of Stresses in Memory Testing
Proceedings of the conference on Design, automation and test in Europe - Volume 2
March iC-: An Improved Version of March C- for ADOFs Detection
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Memory Fault Modeling Trends: A Case Study
Journal of Electronic Testing: Theory and Applications
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
Journal of Electronic Testing: Theory and Applications
Proceedings of the 42nd annual Design Automation Conference
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories
Journal of Electronic Testing: Theory and Applications
Automatic march tests generations for static linked faults in SRAMs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Crosstalk Induced Fault Analysis and Test in DRAMs
Journal of Electronic Testing: Theory and Applications
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions
Journal of Electronic Testing: Theory and Applications
Minimal March Tests for Detection of Dynamic Faults in Random Access Memories
Journal of Electronic Testing: Theory and Applications
Slow write driver faults in 65nm SRAM technology: analysis and March test solution
Proceedings of the conference on Design, automation and test in Europe
Techniques for Disturb Fault Collapsing
Journal of Electronic Testing: Theory and Applications
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits
Journal of Electronic Testing: Theory and Applications
A design-for-diagnosis technique for SRAM write drivers
Proceedings of the conference on Design, automation and test in Europe
Analysis of resistive-open defects in SRAM sense amplifiers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time
Journal of Electronic Testing: Theory and Applications
Analysis of Resistive Open Defects in Drowsy SRAM Cells
Journal of Electronic Testing: Theory and Applications
Deriving a unified fault taxonomy for event-based systems
Proceedings of the 6th ACM International Conference on Distributed Event-Based Systems
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes
Journal of Electronic Testing: Theory and Applications
Impact of resistive-open defects on the heat current of TAS-MRAM architectures
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents a notation for describing functional fault models, which may occur in memory devices. Using this notation, the space of all possible memory faults has been constructed. It has been shown that this space is infinite, and contains the currently established functional fault models. New fault models in this space have been identified and verified using resistive and capacitive defect injection and simulation of a DRAM model.