Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
Open Defects in CMOS RAM Address Decoders
IEEE Design & Test
Resistance Characterization for Weak Open Defects
IEEE Design & Test
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test and Testability Techniques for Open Defects in RAM Address Decoders
EDTC '96 Proceedings of the 1996 European conference on Design and Test
False write through and un-restored write electrical level fault models for SRAMs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories
MTDT '00 Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing
Functional Memory Faults: A Formal Notation and a Taxonomy
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Testing for Resistive Opens and Stuck Opens
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Importance of Dynamic Faults for New SRAM Technologies
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
Journal of Electronic Testing: Theory and Applications
Proceedings of the 42nd annual Design Automation Conference
Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests
MTDT '06 Proceedings of the 2006 IEEE International Workshop on Memory Technology, Design, and Testing
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Capturing dynamic and hard to detect faults in static embedded memories is a significant challenge for DFT designers. Not only it demands at-speed testing, it also requires a large number of operations (generally greater than 24 consecutive reads per memcell) on each memory cell, which is hard to achieve at lower testing budgets. We present a comprehensive study done on resistive defects which lead to read recovery faults in 6T memcell SRAMs. A novel DFT technique has been proposed using calibrated variation in dummy path of self timed memories to capture hard to detect resistive faults in small number of operations. Results show 89% reduction in test time for a robust test on an industrial SRAM with 2048 words operating at 400 MHz.