Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation

Authors:
Keith Baker;Guido Gronthoud;Maurice Lousberg;Ivo Schanstra;Charles Hawkins
Affiliations:
-;-;-;-;-
Venue:
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Year:
1999

Citing 13
Cited 34

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
IDDQ and AC Scan: The War Against Unmodelled Defects

Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ Characterization in Submicron CMOS

Proceedings of the IEEE International Test Conference
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs

Proceedings of the IEEE International Test Conference
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment

Proceedings of the IEEE International Test Conference
Delay Test: The Next Frontier for LSSD Test Systems

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
High volume microprocessor test escapes, an analysis of defects our tests are missing

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Correlations between path delays and the accuracy of performance prediction

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detecting resistive shorts for CMOS domino circuits

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay test generation

DAC '77 Proceedings of the 14th Design Automation Conference
Defect classes - an overdue paradigm for CMOS IC testing

ITC'94 Proceedings of the 1994 international conference on Test
On the detection of delay faults

ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On the fault coverage of gate delay fault detecting tests

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Test generation for resistive opens in CMOS

Proceedings of the 12th ACM Great Lakes symposium on VLSI
Detectability Conditions of Full Opens in the Interconnections

Journal of Electronic Testing: Theory and Applications
Enhancing test efficiency for delay fault testing using multiple-clocked schemes

Proceedings of the 39th annual Design Automation Conference
Deep Submicron CMOS Current IC Testing: Is There a Future?

IEEE Design & Test
Resistance Characterization for Weak Open Defects

IEEE Design & Test
On theoretical and practical considerations of path selection for delay fault testing

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models

Proceedings of the 40th annual Design Automation Conference
DELAY-FAULT TESTING AND DEFECTS IN DEEP SUB-MICRON ICS - DOES CRITICAL RESISTANCE REALLY MEAN ANYTHING?

ITC '00 Proceedings of the 2000 IEEE International Test Conference
A BIST Approach for Very Deep Sub-Micron (VDSM) Defects

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiple-Output Propagation Transition Fault Test

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing for Resistive Opens and Stuck Opens

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Detection of Temperature Sensitive Defects Using ZTC

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Re-synthesis for delay variation tolerance

Proceedings of the 41st annual Design Automation Conference
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Defect Aware Test Patterns

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Journal of Electronic Testing: Theory and Applications
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 μm and 90 nm technologies

Proceedings of the 42nd annual Design Automation Conference
Detection of multiple transitions in delay fault test of SPARC64 microprocessor

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Delay defect screening for a 2.16GHz SPARC64 microprocessor

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Delay variation tolerance for domino circuits

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Experience in critical path selection for deep sub-micron delay test and timing validation

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Via Distribution Model for Yield Estimation

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Interactive presentation: Pulse propagation for the detection of small delay defects

Proceedings of the conference on Design, automation and test in Europe
Design-for-test techniques for opens in undetected branches in CMOS latches and flip-flops

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs

Journal of Electronic Testing: Theory and Applications
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines

Journal of Electronic Testing: Theory and Applications
Testing resistive opens and bridging faults through pulse propagation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Graph partition based path selection for testing of small delay defects

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
On-Chip Delay Measurement Based Response Analysis for Timing Characterization

Journal of Electronic Testing: Theory and Applications
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time

Journal of Electronic Testing: Theory and Applications
Clock-skew test module for exploring reliable clock-distribution under process and global voltage-temperature variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level impact of chip-level failure mechanisms and screens

Proceedings of the International Conference on Computer-Aided Design
A high-precision on-chip path delay measurement architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AC-plus scan methodology for small delay testing and characterization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This defect-based study analyzes statisticalsignal delay properties and delay fault test patternconstraints in the CMOS deep submicron environment.Delay fault testing has uncertainty, or noise, in its attemptto detect defects that slow a signal.CMOS resistive viasand contacts were used as a delay defect target.Datawere taken from a scan-based test chip (Veqtor) on thePhilips 0.25 µm technology.Methods to improve delayfault defect detection are given.