Advanced routing in changing technology landscape
Proceedings of the 2003 international symposium on Physical design
A Simple via Duplication Tool for Yield Enhancement
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Toward PDN resource estimation: a law of general power density
Proceedings of the System Level Interconnect Prediction Workshop
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In this paper, we propose a via distribution model for yield estimation. The proposed model expresses a relationship between the number of vias and wire length. We can also estimate the total number of vias in a circuit, which is derived from the via distribution and the wire-length distribution. The via distribution is modeled as a function of track utilization, and the wire-length distribution can be derived from a gate-level netlist and layout area. We extract model parameters from the commercial chips designed for 0.18-ìm and 0.13-ìm CMOS processes, and demonstrate yield degradation caused by vias.