Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Via Distribution Model for Yield Estimation
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Modeling and analysis of power distribution networks in 3-D ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The power distribution network (PDN) is an increasingly significant consumer of on-chip interconnect resources. Thus, PDN estimation is increasingly central to system-level interconnect prediction for modern ICs. PDN design and verification require accurate power estimation and realistic current source distribution across a die. However, at early design stages, detailed placement or switching information is rarely available, so that designers either rely on pessimistic overdesign, which can lead to severe routing congestion, or encounter unexpected voltage noise problems at late design stages, which can lead to costly design iterations. In this work, we seek to identify a general trend for power density. From both empirical and analytical studies on random activity distributions, we propose a power law of activity density, which can potentially enable estimates of power density and voltage noise, as well as of required power distribution network (PDN) resources, in early design stages.