Requirements for models of achievable routing
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Efficient representation of interconnection length distributions using generating polynomials
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Wiring layer assignments with consistent stage delays
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
A priori system-level interconnect prediction: Rent's rule and wire length distribution models
Proceedings of the 2001 international workshop on System-level interconnect prediction
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
On rent's rule for rectangular regions
Proceedings of the 2001 international workshop on System-level interconnect prediction
Interconnect prediction for programmable logic devices
Proceedings of the 2001 international workshop on System-level interconnect prediction
Pre-layout prediction of interconnect manufacturability
Proceedings of the 2001 international workshop on System-level interconnect prediction
Toward better wireload models in the presence of obstacles
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Terminal optimization analysis for functional block re-use
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Stochastic wire length sampling for cycle time estimation
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Wire layer geometry optimization using stochastic wire sampling
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
A differential equation for placement analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Impact of three-dimensional architectures on interconnects in gigascale integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Toward better wireload models in the presence of obstacles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A probabilistic approach to clock cycle prediction
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Fast estimation of the partitioning rent characteristic using a recursive partitioning model
Proceedings of the 2003 international workshop on System-level interconnect prediction
A-priori wirelength and interconnect estimation based on circuit characteristics
Proceedings of the 2003 international workshop on System-level interconnect prediction
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Improved a priori terconnect predictions and technology extrapolation in the GTX system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Multi-objective optimization of interconnect geometry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
A priori wire length distribution models with multiterminal nets
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Prelayout interconnect yield prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Refinements of Rent's Rule Allowing Accurate Interconnect Complexity Modeling
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Interconnect width selection for deep submicron designs using the table lookup method
Proceedings of the 2004 international workshop on System level interconnect prediction
Prediction of interconnect adjacency distribution: derivation, validation, and applications
Proceedings of the 2004 international workshop on System level interconnect prediction
Prediction of interconnect net-degree distribution based on Rent's rule
Proceedings of the 2004 international workshop on System level interconnect prediction
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An electromigration and thermal model of power wires for a priori high-level reliability prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Calibration of rent's rule models for three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Individual wire-length prediction with application to timing-driven placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential delay budgeting with interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Assessment of on-chip wire-length distribution models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
Proceedings of the 2005 international workshop on System level interconnect prediction
Replacing global wires with an on-chip network: a power analysis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Analysis and evaluation of a hybrid interconnect structure for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2006 international workshop on System-level interconnect prediction
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IBM Journal of Research and Development - POWER5 and packaging
Adaptable wire-length distribution with tunable occupation probability
Proceedings of the 2007 international workshop on System level interconnect prediction
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Impact of interconnect length changes on effective materials properties (dielectric constant)
Proceedings of the 2007 international workshop on System level interconnect prediction
A novel net-degree distribution model and its application to floorplanning benchmark generation
Integration, the VLSI Journal
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Efficient tiling patterns for reconfigurable gate arrays
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Efficient tiling patterns for reconfigurable gate arrays
Proceedings of the 2008 international workshop on System level interconnect prediction
The next resource war: computation vs. communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Rent's rule and parallel programs: characterizing network traffic behavior
Proceedings of the 2008 international workshop on System level interconnect prediction
Energy and switch area optimizations for FPGA global routing architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Using circuit structural analysis techniques for networks in systems biology
Proceedings of the 11th international workshop on System level interconnect prediction
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
Floorplan-based FPGA interconnect power estimation in DSP circuits
Proceedings of the 11th international workshop on System level interconnect prediction
Automated model generation for complex systems
MIC '08 Proceedings of the 27th IASTED International Conference on Modelling, Identification and Control
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
A benchmark diagnostic model generation system
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans - Special issue on model-based diagnostics
Cut-demand based routing resource allocation and consolidation for routability enhancement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Toward five-dimensional scaling: how density improves efficiency in future computers
IBM Journal of Research and Development
Interconnect estimation for mesh-based reconfigurable computing
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Toward PDN resource estimation: a law of general power density
Proceedings of the System Level Interconnect Prediction Workshop
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
Implications of electronics technology trends to algorithm design
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
On the asymptotic costs of multiplexer-based reconfigurability
Proceedings of the 49th Annual Design Automation Conference
Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
Handling global traffic in future CMP NoCs
Proceedings of the International Workshop on System Level Interconnect Prediction
Towards development of an analytical model relating FPGA architecture parameters to routability
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper provides a review of both Rent's rule and the placement models derived from it. It is proposed that the power-law form of Rent's rule, which predicts the number of terminals required by a group of gates for communication with the rest of the circuit, is a consequence of a statistically homogeneous circuit topology and gate placement. The term "homogeneous" is used to imply that quantities such as the average wire length per gate and the average number of terminals per gate are independent of the position within the circuit. Rent's rule is used to derive a variety of net length distribution models and the approach adopted in this paper is to factor the distribution function into the product of an occupancy probability distribution and a function which represents the number of valid net placement sites. This approach places diverse placement models under a common framework and allows the errors introduced by the modeling process to be isolated and evaluated. Models for both planar and hierarchical gate placement are presented.