Modeling the influence of multilevel interconnect on chip performance
Modeling the influence of multilevel interconnect on chip performance
Why interconnect prediction doesn't work
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Wire layer geometry optimization using stochastic wire sampling
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
The future of interconnection technology
IBM Journal of Research and Development
Wire layer geometry optimization using stochastic wire sampling
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
A probabilistic approach to clock cycle prediction
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Toward the accurate prediction of placement wire length distributions in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2005 international workshop on System level interconnect prediction
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Cycle time models perform an a-priori calculation of local signal delays by estimating the lengths of wires connecting different levels of synchronously clocked logic elements. Typically, a signal will have to pass through approximately 15-25 layers of logic during a single clock cycle and it is has been assumed that this number is sufficiently large to allow average wire lengths to be used. This paper investigates the accuracy of this mean value assumption by comparing cycle times calculating using average wire lengths with cycle times calculated using wires sampled from an estimate of the wire length distribution in each wiring layer. The sampling algorithm provides a more accurate calculation of the cycle time and also an estimate of its variation due to the inherently stochastic nature of the layout process. Results for a benchmark netlist, implemented in 0.25 &mgr;m technology, indicate that for a logic depth of 25 the mean value assumption is satisfactory and that clock rate has a standard deviation of approximately 5% of this mean value due to the inherently stochastic nature of the layout process.