Requirements for models of achievable routing
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A performance optimization method by gate sizing using statistical static timing analysis
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
Pre-layout prediction of interconnect manufacturability
Proceedings of the 2001 international workshop on System-level interconnect prediction
Stochastic wire length sampling for cycle time estimation
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Toward the accurate prediction of placement wire length distributions in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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When developing new technologies, it is important to have an indication of the gain that can be achieved by exploring different research directions. Part of this gain is measured by achievable system performance. In this paper, we focus on the a priori prediction of clock speed as a measure for system performance.Previous approaches to clock cycle prediction were based on the summation of a number of (predicted) wire delays, equal to the maximum logic depth in a circuit. However, these methods do not consider the fact that the minimum clock cycle is determined by the largest combinatorial delay that occurs in a very complex and parallel interconnection topology. Indeed, in most circuits, there are a large number of paths with maximum or almost maximum logic depth. When implementing those circuits, any of these paths might become the path with maximal delay.In this paper, we present a new probabilistic model for predicting the maximal combinatorial path delay that partially captures the impact of the parallelism, present in real circuits. Our model is based on the distributions of the sum and of the maximum of a number of independent random variables. We experimentally validate our model using measured wire delay distributions.