The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Performance analysis and technology of 3-D ICs
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
GTX: the MARCO GSRC technology extrapolation system
Proceedings of the 37th Annual Design Automation Conference
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
Getting more out of Donath's hierarchical model for interconnect prediction
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Stochastic wire length sampling for cycle time estimation
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Toward better wireload models in the presence of obstacles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A probabilistic approach to clock cycle prediction
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Fast estimation of the partitioning rent characteristic using a recursive partitioning model
Proceedings of the 2003 international workshop on System-level interconnect prediction
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Energy and switch area optimizations for FPGA global routing architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Using circuit structural analysis techniques for networks in systems biology
Proceedings of the 11th international workshop on System level interconnect prediction
Fast, accurate a priori routing delay estimation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
Interconnect length estimation in VLSI designs: a retrospective
Proceedings of the 2014 on International symposium on physical design
| Hi-index | 0.00 |
Since its introduction, Donath's technique for predicting placement wire length distributions has become one of the most popular techniques for a priori wire length estimation. However, in its original form, it was heavily constrained by the underlying circuit and architecture models. In this paper, we show how a careful relaxation of those constraints results in very high correlations between predicted and experimentally measured average wire lengths as well as, a much improved accuracy in predicting wire length distributions. Because the availability of the Rent characteristic is crucial for the quality of our model, we investigate how the prediction quality degrades when only an estimated characteristic is available. Such an estimation can be required to save computation time or when the complete netlist is not yet available (partial use of typical values). It turns out that a fitted β-model, based on only a few partitioning levels, can still result in a relatively high-prediction quality. In particular, with respect to the wire length distribution, the results are considerably better than when Rent's Rule is used.