Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Topological Properties of Hypercubes
IEEE Transactions on Computers
Locality, communication, and interconnect length in multicomputers
SIAM Journal on Computing
“Hypermeshes”: optical interconnection networks for parallel computing
Journal of Parallel and Distributed Computing
IEEE Transactions on Parallel and Distributed Systems
Folded Petersen Cube Networks: New Competitors for the Hypercubes
IEEE Transactions on Parallel and Distributed Systems
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Design challenges for 0.1um and beyond: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Rent's rule based switching requirements
Proceedings of the 2001 international workshop on System-level interconnect prediction
The computer and the brain
Challenges in physical chip design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The Hyper-deBruijn Networks: Scalable Versatile Architecture
IEEE Transactions on Parallel and Distributed Systems
Beyond Moore's Law: The Interconnect Era
Computing in Science and Engineering
MICCAI '02 Proceedings of the 5th International Conference on Medical Image Computing and Computer-Assisted Intervention-Part I
Interconnect Technology and Design for Gigascale Integration
Interconnect Technology and Design for Gigascale Integration
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Toward the accurate prediction of placement wire length distributions in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Calibration of rent's rule models for three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Global interconnect design in a three-dimensional system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unifying mesh- and tree-based programmable interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
Proceedings of the 2005 international workshop on System level interconnect prediction
Wire Length Distribution Model Considering Core Utilization for System on Chip
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Exact Solution for the Optimal Neuronal Layout Problem
Neural Computation
IBM Journal of Research and Development - POWER5 and packaging
Control Theory and Fast Marching Techniques for Brain Connectivity Mapping
CVPR '06 Proceedings of the 2006 IEEE Computer Society Conference on Computer Vision and Pattern Recognition - Volume 1
Quantifying Human Brain Connectivity from Diffusion Tensor MRI
Journal of Mathematical Imaging and Vision
Networks on chips: keeping up with rent's rule and moore's law
Proceedings of the 2007 international workshop on System level interconnect prediction
Impact of interconnect length changes on effective materials properties (dielectric constant)
Proceedings of the 2007 international workshop on System level interconnect prediction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Editorial to special issue on reliable computing
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Communication Structures for Large Networks of Microcomputers
IEEE Transactions on Computers
Generalized Hypercube and Hyperbus Structures for a Computer Network
IEEE Transactions on Computers
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Brain-scale simulation of the neocortex on the IBM Blue Gene/L supercomputer
IBM Journal of Research and Development
Assessing random dynamical network architectures for nanoelectronics
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
On brain-inspired connectivity and hybrid network topologies
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
A view of the parallel computing landscape
Communications of the ACM - A View of Parallel Computing
Using circuit structural analysis techniques for networks in systems biology
Proceedings of the 11th international workshop on System level interconnect prediction
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Life-Inspired systems and their quality-driven design
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
IEEE Spectrum
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This research compares the brain's connectivity (based on different analyses of neurological data) with well-known network topologies (originally used in super-computers) using Rent's rule. The comparison reveals that brain connectivity is in good agreement with Rent's rule. However, the known network topologies fall short of being strong contenders for mimicking brain's connectivity. That is why we perform a detailed Rent-based (top-down) connectivity analysis of generic two-layer hierarchical network topologies. This analysis aims to identify generic two-layer hierarchical network topologies which could closely mimic brain's connectivity. The range of granularities (i.e., number of gates/cores/neurons) where such mimicking is possible are identified and discussed. These results should have implications for the design of future networks-on-chip in general, and for the burgeoning field of multi/many-core processors in particular (in the medium term), as well as for forward-looking investigations on emerging brain-inspired nano-architectures (in the long run).