Interconnect opportunities for gigascale integration
IBM Journal of Research and Development
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Hybrid nanoelectronics: future of computer technology
Journal of Computer Science and Technology
Prediction in electronics based on limited information
EHAC'09 Proceedings of the 8th WSEAS international conference on Electronics, hardware, wireless and optical communication
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Throughput optimization for latency-insensitive system with minimal queue insertion
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compressive sensing with local geometric features
Proceedings of the twenty-seventh annual symposium on Computational geometry
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
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Increases in transistors per chip will advance interconnect technology, and when nanoelectronics replace silicon as the technology of choice, the interconnect era will truly begin.