Optical Clock Distribution in Electronic Systems
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Digital systems engineering
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
A compact physical via blockage model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
The future of interconnection technology
IBM Journal of Research and Development
Beyond Moore's Law: The Interconnect Era
Computing in Science and Engineering
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Investigation of performance metrics for interconnect stack architectures
Proceedings of the 2004 international workshop on System level interconnect prediction
Physical limitations on the bit-rate of on-chip interconnects
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Silicon carrier for computer systems
Proceedings of the 43rd annual Design Automation Conference
IBM Journal of Research and Development - POWER5 and packaging
Optimizing CMOS technology for maximum performance
IBM Journal of Research and Development - Advanced silicon technology
3D chip stacking with C4 technology
IBM Journal of Research and Development
SSMCB: low-power variation-tolerant source-synchronous multicycle bus
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Advanced Cu interconnects using air gaps
Microelectronic Engineering
Quality factor and frequency bandwidth of 2D self-inductors in 3D integration stacks
Microelectronic Engineering
Large-scale integrated photonics for high-performance interconnects
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design of multi-channel wireless NoC to improve on-chip communication capacity
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Toward five-dimensional scaling: how density improves efficiency in future computers
IBM Journal of Research and Development
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Throughout the past four decades, semiconductor technology has advanced at exponential rates in both productivity and performance. In recent years, multilevel interconnect networks have become the primary limit on the productivity, performance, energy dissipation, and signal integrity of gigascale integration. Consequently, a broad spectrum of novel solutions to the multifaceted interconnect problem must be explored. Here we review recent salient results of this exploration. Based upon prediction of the complete stochastic signal interconnect length distribution of a megacell, optimal reverse scaling of each pair of wiring levels provides a prime opportunity to minimize cell area, clock period, power dissipation, or number of wiring levels. Using a heterogeneous version of Rent's rule, a design methodology for the global signal, clock, and power/ground distribution networks for a system-on-a-chip has been derived. Wiring area, bandwidth, and signal integrity are the prime constraints on the design of the networks. Three-dimensional integration offers the opportunity to reduce the length of the longest global interconnects in a distribution by as much as 75%. Wafer-level batch fabrication of chip input/output interconnects and chip scale packages provides new benefits such as I/O bandwidth enhancement, simultaneous switching-noise reduction, and lower cost of packaging and testing. Microphotonic interconnects have long-term potential to reduce latency, power dissipation, and crosstalk while increasing bandwidth.