A compact physical via blockage model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Throughput-driven IC communication fabric synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Novel Metric for Interconnect Architecture Performance
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Interconnect opportunities for gigascale integration
IBM Journal of Research and Development
Package level interconnect options
Proceedings of the 2005 international workshop on System level interconnect prediction
Wafer-level package interconnect options
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper discusses metrics involving the bandwidth and energy characteristics of arbitrary interconnect stacks. Front-end dimensions are set by lithography and related fabrication restrictions and its performance is easily quantified using well-known metrics such as FO4 or ring oscillator delays, Ioff, and Ion. Back-end dimensions are not similarly constrained yet there are no comparable back-end metrics. In this study we seek figures-of-merit for interconnect architectures (stacks) that describe performance in terms of bandwidth and energy while considering issues such as via blockage and repeaters. A definition of bandwidth is presented and then appropriate via blockage models for interconnect stacks are investigated. In this paper, we improve existing bandwidth and throughput-driven design methodologies by looking at the entire stack rather than a single wiring layer. We also propose the use of bandwidth per unit energy. We evaluate and discuss these metrics in current 130nm and 90nm interconnect technologies.