Hierarchical Interconnects for On-Chip Clustering
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
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ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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Proceedings of the 2004 international workshop on System level interconnect prediction
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Proceedings of the 2004 international workshop on System level interconnect prediction
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Proceedings of the 2006 international workshop on System-level interconnect prediction
Constant Impedance Scaling Paradigm for Scaling LC transmission lines
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Analysis and modeling of power grid transmission lines
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Analysis and modeling of power grid transmission lines
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Scaling enhances intrinsic transistor performance and degrades interconnects. As the technology steps into nanometer era, global interconnects are becoming bottleneck for overall chip performance. In this paper, we show package level interconnects are an effective alternative for on-chip global wiring. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance - bandwidth, bandwidth density, latency and power consumption - of the package level transmission lines with conventional on-chip global interconnects for different ITRS technology nodes. Based on these results, we show package level interconnects are well suited for power demanding low latency applications and we analyze different interconnect options like memory buses, long inter tile interconnects, clock and power distribution.