Chip and Package Co-Design Technique for Clock Networks

Authors:
Qing Zhu;Wayne W. M. Dai
Affiliations:
-;-
Venue:
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Year:
1996

Citing 0
Cited 3

A Flip-Chip Implementation of the Data Encryption Standard (DES)

MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Package level interconnect options

Proceedings of the 2005 international workshop on System level interconnect prediction
Wafer-level package interconnect options

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents the motivation and a case study for a new clock distribution technique: route the global clock on package. This technique can be used in single chips and multichip modules based on area I/Os of the flip chip technology. Due to 2-4 order lower interconnect resistance on package layers, the clock skew and path delay of the clock network are significantly reduced.