Interconnect Energy Dissipation in High-Speed ULSI Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Chip and Package Co-Design Technique for Clock Networks
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Investigation of performance metrics for interconnect stack architectures
Proceedings of the 2004 international workshop on System level interconnect prediction
Constant Impedance Scaling Paradigm for Scaling LC transmission lines
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Analysis and modeling of power grid transmission lines
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Analysis and modeling of power grid transmission lines
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An RDL-configurable 3D memory tier to replace on-chip SRAM
Proceedings of the Conference on Design, Automation and Test in Europe
Wafer warpage analysis of stacked wafers for 3D integration
Microelectronic Engineering
Wafer level package with thermal-stress-absorbing interface structure and elongated pad
Microelectronic Engineering
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As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performance measures such as bandwidth, bandwidth density, latency, and power consumption of the package-level transmission lines with conventional on-chip global interconnects for different International Technology Roadmap for Semiconductors (ITRS) technology nodes. Based on these results, we show that package-level interconnects are well suited for power demanding low-latency applications. We also analyze different interconnect options such as memory buses, long inter tile interconnects, clock, and power distribution.