Hierarchical Interconnects for On-Chip Clustering
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Package level interconnect options
Proceedings of the 2005 international workshop on System level interconnect prediction
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
Constant impedance scaling paradigm for interconnect synthesis
Proceedings of the 2006 international workshop on System-level interconnect prediction
Electrical interconnects revitalized
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wafer-level package interconnect options
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reverse scaled LC transmission lines are an effective alternative to on-chip global interconnects which severely limit the chip performance in nano-CMOS technologies. However, the main disadvantage of the LC transmission line approach is their poor wiring density. The scaling of LC transmission lines is formally analyzed with the proposed constant impedance scaling paradigm that simultaneously maximize performance and wiring density. With this paradigm, we show that the LC transmission line implementation would need a minimum pitch of 8um for line lengths in the range of 10 to 20 mm, considering a low-k dielectric of relative dielectric constant of 2.7.