Constant impedance scaling paradigm for interconnect synthesis

Authors:
J. Balachandran;S. Brebels;G. Carchon;M. Kuijk;W. De Raedt;B. Nauwelaers;E. Beyne
Affiliations:
Microwave and RF Systems Group, Leuven, Belgium;Microwave and RF Systems Group, Leuven, Belgium;Microwave and RF Systems Group, Leuven, Belgium;Vrije Universiteit Brussel, Brussel, Belgium;Microwave and RF Systems Group, Leuven, Belgium;Katholieke Universiteit Leuven, Leuven, Belgium;Microwave and RF Systems Group, Leuven, Belgium
Venue:
Proceedings of the 2006 international workshop on System-level interconnect prediction
Year:
2006

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Abstract

On-chip global interconnects perceived as performance limiters for continued scaling of integrated circuits in nano-CMOS regimes highlight the importance of their proper design and optimization. A constant impedance scaling paradigm is proposed for systematic synthesis of complete interconnects physical parameters from system level performance metrics such as delay, power and wiring density. The methodology is illustrated for different system level targets and optimal physical parameters are deduced.