Requirements for models of achievable routing
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Wiring layer assignments with consistent stage delays
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A compact physical via blockage model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Maximum multiplicity distributions (MMD)
Proceedings of the 2003 international workshop on System-level interconnect prediction
Investigation of performance metrics for interconnect stack architectures
Proceedings of the 2004 international workshop on System level interconnect prediction
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI)
Proceedings of the 2004 international workshop on System level interconnect prediction
A Novel Metric for Interconnect Architecture Performance
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Proceedings of the 2006 international workshop on System-level interconnect prediction
Constant impedance scaling paradigm for interconnect synthesis
Proceedings of the 2006 international workshop on System-level interconnect prediction
IntSim: A CAD tool for optimization of multilevel interconnect networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Design and optimization of on-chip interconnects using wave-pipelined multiplexed routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On pioneering nanometer-era routing problems
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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A multilevel interconnect architecture design methodology that optimizes the interconnect cross-sectional dimensions of each metal layer is introduced that reduces logic macrocell area, cycle time, power consumption or number of metal layers. The predictive capability of this methodology, which is based on a stochastic wiring distribution, provides insight into defining the process technology parameters for current and future generations of microprocessors and application-specific integrated circuits (ASICs). Using this methodology on an ASIC logic macrocell case study for the 100-nm technology generation, the optimized n-tier mulilevel interconnect architecture reduces macrocell area by 32%, cycle time by 16% or number of wiring tracks required on the topmost tier by 62% compared to a conventional design where pitches are doubled for every successive pair of levels. A new repeater insertion methodology is also described that further enhances gigascale integration (GSI) system performance. By using repeaters, a further reduction of 70% in macrocell area, 18% in cycle time, 25% in number of metal levels or 44% in power dissipation is achieved, when compared to an n-tier design without repeaters. The key distinguishing feature of the methodology is its comprehensive framework that simultaneously solves two distinct problems - optimal wire sizing and wiring layer assignment - using independent constraints on maximum repeater area for efficient deisgn space exploration to optimize the repeater area for efficient design space exploration to optimized the area, power, frequency, and metal levels of a GSI logic megacell