Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of throughput performance for low-power VLSI interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Global interconnections in FPGAs: modeling and performance analysis
Proceedings of the 2008 international workshop on System level interconnect prediction
Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Wave-pipelined intra-chip signaling for on-FPGA communications
Integration, the VLSI Journal
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultra-low-power signaling challenges for subthreshold global interconnects
Integration, the VLSI Journal
Semi-serial on-chip link implementation for energy efficiency and high throughput
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Every new VLSI technology generation has resulted in interconnects increasingly limiting the performance, area, and power dissipation of new processors. Subsequently, it is necessary to devise efficient interconnect design techniques to reduce the impact of VLSI interconnects on overall system design. New optimizations of a wave-pipelined multiplexed (WPM) interconnect routing circuit are described in this paper. These WPM circuits can be used with current interconnect repeater circuits to further reduce interconnect delay, interconnect area, transistor area, and/or power dissipation. For example, new area constrained WPM circuit optimizations illustrate that the interconnect circuit power can be reduced by 26% or the interconnect performance can be improved by 74%. Moreover, in both these cases, because a significant number of repeaters are eliminated, the transistor area can reduce by 41% or 29%, respectively. Finally, the tolerance of WPM circuits to crosstalk noise, power supply noise, clock skew, and manufacturing variations is also presented. This study of tolerance levels defines the conditions under which the WPM circuit will function correctly, and it is shown in this paper for the first time that WPM circuits are robust enough to operate with variability that can be encountered in deep submicrometer technologies.