Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Variation-driven device sizing for minimum energy sub-threshold circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Design and optimization of on-chip interconnects using wave-pipelined multiplexed routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scaling and evaluation of carbon nanotube interconnects for VLSI applications
Proceedings of the 2nd international conference on Nano-Networks
Temperature effects on energy optimization in sub-threshold circuit design
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits
Extreme Low-Power Mixed Signal IC Design: Subthreshold Source-Coupled Circuits
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Demand of power efficient circuits has grown significantly due to fast growth of battery operated portable applications. Though, subthreshold operation of device shows huge potential towards satisfying the ULP requirement, it holds many challenging design issues. As integration density of interconnect increases at every technology node, increased delay and crosstalk become more challenging design issues particularly for subthreshold interconnects. Nanometer subthreshold interconnect faces subthreshold driver design challenges and problems due to increased interconnect capacitance. This paper explored the suitability of different conventional interconnects strategies and challenges to reduce the total path delay. It also proposed device and interconnect optimization techniques to achieve higher performance and to reduce crosstalk in future subthreshold global interconnects. The effect of variability on subthreshold interconnects have also been investigated.