Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS
Proceedings of the 2004 international symposium on Low power electronics and design
Device optimization for ultra-low power digital sub-threshold operation
Proceedings of the 2004 international symposium on Low power electronics and design
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents
Proceedings of the 42nd annual Design Automation Conference
A variation tolerant subthreshold design approach
Proceedings of the 42nd annual Design Automation Conference
Minimum Energy Near-threshold Network of PLA based Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Robust Design of High Fan-In/Out Subthreshold Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A Feasibility Study of Subthreshold SRAM Across Technology Generations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A PLA based asynchronous micropipelining approach for subthreshold circuit design
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing reverse short channel effect for optimal subthreshold circuit design
Proceedings of the 2006 international symposium on Low power electronics and design
Logic circuits operating in subthreshold voltages
Proceedings of the 2006 international symposium on Low power electronics and design
Interactive presentation: Process tolerant β-ratio modulation for ultra-dynamic voltage scaling
Proceedings of the conference on Design, automation and test in Europe
Soft-well digital circuit design
Proceedings of the 20th annual conference on Integrated circuits and systems design
Utilizing reverse short-channel effect for optimal subthreshold circuit design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy
Journal of Electronic Testing: Theory and Applications
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
New performance/power/area efficient, reliable full adder design
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5fJ/stage PDP
Microelectronics Journal
UV-programmable Floating-Gate CMOS Linear Threshold Element "P1N3"
IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Improving power-delay performance of ultra-law-power subthreshold SCL circuits
IEEE Transactions on Circuits and Systems II: Express Briefs
Leakage current reduction using subthreshold source-coupled logic
IEEE Transactions on Circuits and Systems II: Express Briefs
Energy-efficient subthreshold processor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A study of sub-threshold digital circuits for wireless communication systems
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
ABRM: adaptive β-ratio modulation for process-tolerant ultradynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CSS'10 Proceedings of the 4th international conference on Circuits, systems and signals
High speed interconnect through device optimization for subthreshold FPGA
Microelectronics Journal
Performance analysis of FPGA interconnect fabric for ultra-low power applications
Proceedings of the 2011 International Conference on Communication, Computing & Security
Performance optimization of CNFET for ultra-low power reconfigurable architecture
Proceedings of the 2011 International Conference on Communication, Computing & Security
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultra-low-power signaling challenges for subthreshold global interconnects
Integration, the VLSI Journal
Ultra low-power neural inspired addition: when serial might outperform parallel architectures
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Robustness comparison of emerging devices for portable applications
Journal of Nanomaterials
Optimization for real-time systems with non-convex power versus speed models
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Interconnect optimization to enhance the performance of subthreshold circuits
Microelectronics Journal
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Digital subthreshold logic circuits can be used for applications in the ultra-low power end of the design spectrum, where performance is of secondary importance. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (Sub-DTMOS) logic. Both logic families have comparable power consumption as regular subthreshold CMOS logic (which is up to six orders of magnitude lower than that of normal strong inversion circuit) with superior robustness and tolerance to process and temperature variations than that of regular subthreshold CMOS logic.